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Scientific Reports volume 13, Article number: 16436 (2023 ) Cite this article current in an inductor
This paper introduces an optimized DC–DC converter that employs a modified switched inductor-capacitor technique to achieve ultra-high voltage gain for renewable energy systems. The development is based on adding one cell of modified switched inductor (MSL1) with series diodes interleaved with the main switch in the proposed DC–DC converter. The (MSL1) with capacitor operates in resonant mode to reduce current stress across the main switch when the charge in capacitor becomes zero. This approach also reduces voltage stress across the main switch, all inductors, and diodes. Furthermore, modified switched inductors (MSL2) with an auxiliary switch and a coupled capacitor are incorporated to provide double boosting voltage and to achieve high voltage gain. Additionally, a main and auxiliary switch are integrated with modified switched capacitors (MSC) to provide ultra-high voltage gain and to reduce voltage stress across auxiliary switch. Moreover, the proposed converter exhibits a continuous input current with zero pulsating, even at very low duty cycles. The advantages of the proposed converter are high efficiency, low voltage stress, and low values of inductors and capacitors when utilizing a high switching frequency. A mathematical model for the proposed converter is developed for both continuous conduction mode and discontinuous conduction mode. In addition, the PCB design for the proposed converter is presented, and experimental tests are conducted to verify the simulation and laboratory results. The proposed converter aims to boost the voltage from 20 to 40 V to a variable output voltage between 200 and 400 V, delivering 400 watts of power with an efficiency of 96.2%.
Over the past few decades, attention has been drawn to the pressing issues of climate change and global warming due to greenhouse gas emissions. As a result, the necessity of reducing carbon emissions from fossil fuels has been recognized1,2,3,4,5,6,7,8. Sustainable energy resources, such as photovoltaic cells, FC fuel cells, and wind energy, are being utilized for electricity generation. However, these sources are characterized by a lower output voltage when compared to the voltage of the main grid connection. To increase the output voltage of photovoltaic cells, they can be connected in series. Nevertheless, a high and stable output voltage is not achieved through this method due to the shadow effect8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29. A suitable solution to this problem is the application of a DC–DC converter. By employing power electronic DC–DC converters with high voltage gain, the output voltage of PV panels can be enhanced12. However, many challenges are faced by researchers in the modification and development of new DC–DC power converters for renewable energy applications. Several conventional DC–DC converters, such as Boost, SEPIC, CUK, ZETA, and Buck Boost converters, are employed to increase low voltage to high voltage gain for various applications like Uninterruptible Power Supply, street LED lights, and medical devices. Nevertheless, these converters come with their own set of problems when utilized for achieving boosted high-voltage gain, as previously mentioned. For instance, a conventional boost converter can operate and boost low voltage up to 10 times the voltage gain6. However, the efficiency of traditional boost converters diminishes after high extreme duty ratios are employed. Additionally, the limited counts of inductors and capacitors render traditional converters unsuitable for ultra-high voltage gain. Furthermore, power MOSFET devices experience high voltage stress and high current stress when the converter operates at a high extreme duty ratio. Moreover, when the converter operates at high voltage with a very high duty ratio, MOSFET conduction and switching power losses significantly increase, along with the issue of reverse recovery due to diodes5. These converters, as mentioned earlier, have attracted the interest of many researchers aiming to achieve high voltage gains. Various topologies have been developed using coupled and non-coupled inductors, isolated and non-isolated transformers to boost voltage gain. Concerning the converters developed using coupled inductors and transformers, a dual boosting stage with a common ground coupled inductor and switched capacitor for RES was proposed in1, while11 combined two conventional CUK and SEPIC converters with coupled inductors for the same purpose. Another development is presented in22, which introduces a Y-source step-up converter based on three coupled inductors for boosting applications. Additionally, Nafari and Beiranvand31 presents an improved Z-source (ZS) converter using a coupled inductor with one core. In32, a modification to a DC–DC converter is proposed using a single-switch SEPIC converter with an isolated transformer and supporting Voltage Doppler (VD) cell, without using a clamped circuit. In27, a modified Z-source (ZS) converter with a unique ground between the energy source and load is discussed, utilizing coupled inductors and a voltage multiplier (VM) for RES applications as non-isolated. Siwakoti et al.25 presents a modified SEPIC converter with a coupled inductor for piezoelectric drive systems, while28 developed a SEPIC converter using a coupled inductor with a passive clamp circuit for high step-up gain converters. Additionally, Kushwaha et al.24 presents a combined conventional Cuk and SEPIC converter developed as a single stage for electric vehicle battery chargers with coupled inductors. These developed converters have been demonstrated to achieve high voltage gain but at the cost of utilizing a high number of inductors and capacitors. Moreover, coupled inductors can result in leakage inductance, leading to a very high spike voltage across the MOSFET during the off-time. This can result in the converter becoming bulky, heavy, and costly. Furthermore, using a higher number of MOSFETs and diodes leads to a significant decrease in converter efficiency, as conduction and switching losses increase. Additionally, increasing the number of turns ratio of the coupled inductor to enhance the voltage gain results in higher internal resistance, which can impair the system's efficiency and performance.
Numerous advancements have been made in non-isolated DC–DC converters to achieve high voltage transfer ratios. In2, a modification to the non-isolated Luo converter is proposed, employing a single switch with a hybrid switched capacitor (SC) technique. In3, a modified Z-source network with a double input DC–DC converter is presented to achieve a high voltage transfer gain. Additionally, Bhaskar et al.4 introduces an Improved Boost Converter as a multistage Switched Inductor that utilizes a polarized capacitor, while5 presents a single switch with a single inductor based on a new hybrid boosting converter (HBC) that employs a bipolar voltage multiplier (BVM) to enhance the voltage conversion ratio. The SEPIC structure has been enhanced by integrating it with a conventional boost using active switched capacitors (ASC) and switched inductors (ASL), as described in10,11,12,13,14,15,16,17,18, resulting in modifications in9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34. Furthermore, Sedaghati et al.8 proposed the use of two interleaved KY converters, and16 combined a KY converter interleaved with a conventional buck converter to form a buck-boost converter for stepping up the output voltage. While high voltage gain can be achieved by these converters, they face limitations when operating at low switching frequencies. Larger inductors and capacitors are necessitated by low switching frequencies, increasing the internal resistance of MOSFETs, leading to higher power losses and reduced efficiency. Additionally, conduction and switching losses can be elevated by a high number of diodes and MOSFETs, further reducing efficiency. The impact on voltage gain values is also exacerbated by the use of diodes with a high forward voltage, contributing to converter performance issues. Other topologies, such as the conventional ZS impedance network converter with (SC) proposed in7, and the modified traditional buck-boost converter with an additional switch in14, have also been suggested. In15, a traditional boost converter was developed by adding a switched network with two conventional four-quadrant switches, while in19, a SC with a diode was added. In17,18,19,20,21,22,23,24,25,26,27,28,29,30, a traditional SEPIC converter is combined with a conventional boost converter and with (n) number of voltage multipliers in26, and an active (SL) combined with passive inductors in12, to achieve high step-up voltage gain. Two traditional SEPIC converters are combined in20,21, a converter with a dual-switch and (SC) is proposed to attain a high voltage gain. Maalandish et al.23 presents two modified three-phase interleaved boost converters, each with two (SC) in every phase, while33 describes a conventional SEPIC converter with a combination of inductors, capacitors, and diodes. These non-isolated converters, designed for use in photovoltaic (PV) applications, have the potential to achieve high conversion ratios. However, as mentioned earlier, lower voltage gain is exhibited by these converters with pulsating input current at low duty cycles. Additionally, complex control circuits are required for the power MOSFETs, and the input current can follow more than one path during the on and off states. Moreover, power MOSFETs and diodes are subjected to high voltage and current stresses during the on and off states. Furthermore, high conduction and switching losses are incurred by these converters at high extreme duty cycles in achieving high voltage gain. Additionally, a high number of switches is required to achieve high voltage gain.
This paper optimized a DC–DC converter that utilizes a modified (MSLSC) technique to achieve ultra-high voltage gain for renewable energy sources (RES). The development is based on adding one cell of (MSL1) (L2 and C1) with series diodes interleaved with the main switch in the proposed DC–DC converter, as shown in Fig. 1b. This MSL1 with capacitor operates in resonant mode to reduce current stress across the main switch when charge in capacitor C1 becomes zero. In addition, this approach also reduces voltage stress across the main, auxiliary switches and diodes (D1, D2, and D3). Furthermore, (MSL2) with an auxiliary switch and a coupled capacitor are incorporated to provide double boosting voltage and achieve high voltage gain. Additionally, main and auxiliary switches are integrated with (MSC) to provide ultra-high voltage gain. Moreover, the proposed converter exhibits a continuous input current with zero pulsating at a very low duty cycle. In addition, D2 and D3 operate in zero voltage switching (ZVS), as shown in Fig. 3c, at minimum input voltage and at high load current. The proposed DC DC converter operate at DCM and CCM with zero pulsating input current at low duty cycle. In addition, the proposed DC–DC converter can supply variable high-output voltage between 200 and 400 V, making it more suitable for a wide range of applications. Furthermore, a dual PI controller is designed for the proposed converter to maintain a fixed output voltage under variable load and input voltage conditions.
(a) Connection of a basic switched inductor, (b) a hybrid connection both a switched inductor and a capacitor (c), the proposed converter connects with PV Panels and Batteries, designed for Energy Saving Mode Applications (d). The structure of proposed DC–DC converter.
The structure of the proposed converter consists of four main low-value inductors, five capacitors, four diodes, and two power MOSFET switches (main and auxiliary) as shown in Fig. 1d. Where the main switch is Sw1 and auxiliary switch is Sw2. The proposed DC–DC converter has been modified to incorporate a basic switched inductor and a hybrid switched inductor-capacitor, as illustrated in Fig. 1a,b. The interconnection between the suggested converter, photovoltaic panels, and a battery, specifically for applications related to energy-saving modes is shown in Fig. 1c. The proposed DC–DC converter has been developed to achieve an ultra-high voltage gain, capable of boosting a low input voltage range of 20–40 V to a variable output voltage between 200 and 400 V under a 400 W load, making the system more suitable for a wide range of applications. The proposed DC–DC converter offers several advantages over previous converters. Firstly, it eliminates the need for isolated coupled inductors and transformers to step up the voltage, resulting in reduced values of inductors and capacitors at high switching frequencies. This enhances the efficiency of the proposed converter. Moreover, the structure of the converter is simple and easy to implement. The proposed converter is also highly reliable for renewable energy system (RES) applications as it ensures no pulsating input current at low duty cycle. In addition, L2 and C1 operate at resonant mode, which reduces the current stress through Sw1 when the charge in capacitor C1 becomes zero at (D-2m), as shown in Fig. 11b,f. In addition, D2 and D3 operate in (ZVS) as shown in Fig. 13c at minimum input voltage and at high load current. Furthermore, the MOSFET switches and diodes experience very low voltage stress. Moreover, the voltage stress across inductors is also reduced when L2 and C1 operate at resonant mode. Additionally, the proposed converter achieves a higher voltage gain at high switching frequency than previous DC–DC converters. It can accommodate a wide range of duty cycles for high-power applications and boost low input voltage to high output voltage at very low duty cycles without the use of coupled inductors and transformers. The PWM generator of the MOSFET switches is simple, and both MOSFET devices turn on and off at the same time. The converter is characterized by its small size, low cost, and high efficiency, achieved by using capacitors and inductors with very small values.
The proposed converter is illustrated in Fig. 1d and is capable of operating in two modes. The first mode, known as DCM, has two conditions: DCMC1 and DCMC2. DCMC1 occurs at the maximum input voltage with four states of operation during one cycle at very low duty ratios. DCMC2 occurs when the converter operates at the minimum input voltage with a duty ratio of approximately 33%, as shown in Fig. 4a,b. The proposed converter can also function in CCM at high load currents when duty ratio is above 70%.
The proposed converter can operate in DCMC1 with five modes of operation, as illustrated in Fig. 3a, which presents the waveform of the proposed converter in DCMC1. This mode appears in light load applications with a duty cycle below 30%, as shown in Fig. 4a, b. In this mode, the input current remains in (CCM) at both low and high duty ratios. Conversely, the current through L3 and L4 operates in (DCM).
Mode 1 [0–t0] Both MOSFETs Sw1 and Sw2 are simultaneously switched on, causing diodes D2, D3, and D4 to be turned off. Energy is linearly charged from the input source Vg by L1 since it is in series with it. L2 is charged from C1 through Sw1. In this mode, D1 is switched on, and capacitors C2 and C3 are connected in series. They are employed to charge L3 through Sw2, while L4 is charged from C4. Energy is provided to the load by C5. The converter for this mode is illustrated in Fig. 2a. Below are the voltage and current equations for the various components in this mode:
where VL is the voltage across the inductor, iL is the current through the inductor, Ic is the current through the capacitor, Io is the output current, ID is the diode current, Vg is the input voltage source, Vo is the output voltage of the proposed converter, Vc is the voltage across the capacitor, and RL is the resistive load.
(a) Mode 1 DCMC1, Mode 1 DCMC2, (b) Mode 2 DCMC1, (c) Mode 3 DCMC1, Mode 4 DCMC2, Mode 4 CCM, (d) Mode 4 DCMC1, Mode 5 DCMC2, Mode 3 DCMC1, (e) Mode 1 DCMC2, Mode 2 DCMC2, Mode 2 CCM , (f) Mode 3 DCMC2,Mode 2 DCMC2, Mode 2 CCM, Mode 3 CCM.
Mode 2 [t0–t1] the power MOSFETs are in the off state as zero gate voltage is provided to them by the Pulse generator to keep them off. Both diodes D2 and D3 are in the on state, and D4 is also in the on state during this mode. L1 will discharge its energy to C1 while charging of C2 and C3 occurs in a nonlinear manner. L2 will begin to discharge its power to C2 and C3. D1 remains in the on state in this mode due to the discharging current of L2 through it. C2 and C3 will start storing a significant amount of energy from L1 and L2. C5 will receive a large amount of energy from L3 and L4 during the discharging time, allowing high power to be supplied to the load. The proposed converter for this mode is depicted in Fig. 2b. Here are the voltage and current equations for the various components in this state:
Mode 3 [t1–t2]: The power MOSFETs are still in the off state, and diodes D2 and D3 remain in the on state. The energy of L1 is discharged nonlinearly due to resonance with C1, resulting in energy transfer to C1 to minimize input current ripple and to charge C2 and C3. During the time (D + m1), L2 is not charged and reaches zero, resulting in ID1 being zero. Energy is continued to be received by C2 and C3 only from L1. Energy continues to be supplied to C5 from L3 and L4 during the discharging period, while high power is still received by the load from C5. The proposed converter for this mode is shown in Fig. 2c. The voltage equations remain the same as in the previous mode, and the current equations for this state are as follows:
Mode 4 [t2–t3]: The power MOSFETs are still in the off state, and only D2 and D3 remain on. In this mode, D4 is turned off, while D1 remains off. The energy stored in L1 is discharged through C1 to charge C2 and C3, which store a large amount of energy for the next gate pulse to supply a substantial amount of energy to the load. L4 will have the same current values as L3 but in opposite directions (iL3 = − iL4). C5 supplies high power to the load. The proposed converter for this mode is shown in Fig. 2d. The waveforms for these four operational modes are illustrated in Fig. 3a.
(a) Time-domain waveforms for the proposed DC–DC converter operating in DCMC1. (b) Time domain waveforms for the proposed DC–DC converter operating in DCMC 2. (c) Time domain waveforms for the proposed DC–DC converter operating in CCM.
When Vg is decreased to its minimum value, the proposed converter can operate in DCMC2 with five modes of operation, as illustrated in Fig. 3b, which presents the waveform of the proposed converter in DCMC2. In this mode, the input current remains in CCM at both low and high duty ratios, while C1 operates in a resonant mode with L2. Conversely, the current through L3 and L4 operates in DCM. This approach effectively reduces the voltage stress across the auxiliary switch, thereby decreasing the losses in the proposed converter.
Mode 1 [0–t0]: Both Sw1 and Sw2 are simultaneously switched on, resulting in the switching off of diodes D2, D3, and D4. L1 accumulates energy linearly from the input source Vg. L2 accumulates energy from C1 through Sw1 until (D-2m), at which point the charge in C1 becomes zero. D1 is switched on, and the capacitors currents C2 and C3 are utilized to charge L3 through Sw2, while L4 charges from C4. C5 supplies energy to the load. The proposed converter for this mode is illustrated in Fig. 2a,e.
Mode 2 [t0–t1]: The power MOSFETs remain in the on state. Both diodes, D2 and D3, turn on during this state because the charge in C1 becomes zero at (D-2 m), as shown in Fig. 3b. Consequently, L2 begins to discharge energy through D2 and D3 to charge L3 and L4. This reduces the current stress through Sw1, as depicted in Fig. 11b. The current through Sw1 is solely sourced from L1. D4 remains off, and L1 continues to accumulate energy from the input voltage source. In this mode, D1 experiences very low voltage stress, implying that L2 acts as an open circuit during the time (D-m). Furthermore, in this mode, D2 and D3 experience (ZVS) across them from ((D-2m) < t < (D-m)). After this time, both of them work as a path to pass the current from L2. L3 and L4 continue to charge from C2, C3 and L2. L2's charge becomes zero at (D-m). C5 still supplies power to the load. The proposed converter for this mode is shown in Fig. 2e,f. The current equations for this state are provided below.
Mode 3 [t1–t2] The Power MOSFETs remain in the "on" state, and both diodes D2 and D3 are still turned on. L2 is treated as an open circuit, with D1 is switched off. L1 continues to charge from the input source, and L3 and L4 will continue to accumulate current from C2 and C3 through Sw2. C5 will begin accumulating a larger amount of energy from L3 and L4 through D4, and this energy will be used to supply power to the load. The proposed converter for this mode is depicted in Fig. 2f. The current equations for this mode are presented in Eq. (18).
Mode 4 [t2–t3] The Power MOSFETs are both turned off, and D2 and D3 remain in the "on" state, while D4 is switched on. L2 is treated as an open circuit in this mode, and L1 is discharging energy to charge C1, C2, and C3 while storing a significant amount of energy to supply to the load. C5 continues to receive energy from L3 and L4 during the discharging period (D1), while the load continues to receive high power from C5. The proposed converter for this mode is illustrated in Fig. 2c.
Mode 5 [t3–t4]: Both MOSFETs remain in the off state, and D2 and D3 are still on. D4 is now turned off. During this period (D2), L3 will carry the same current as L4 but in opposite directions: iL3 = − iL4. The load will receive a high amount of energy from C5. The proposed converter for this mode is depicted in Fig. 2d.
This mode is activated when the load current surpasses a 70% duty cycle, as depicted in Fig. 4, and when the load factor (k) exceeds the critical value of K (Kcrit). In this mode, the proposed converter maintains the input current in CCM, with L2 still operating in resonance mode with C1, and the current through L3 and L4 also remains in CCM. Furthermore, the voltage transfer ratio in this mode experiences a significant increase. When the proposed converter operates in CCM, it exhibits four distinct modes of operation. The time-domain waveforms for the proposed DC–DC converter operating in CCM are also illustrated in Fig. 3c.
Dynamic response of the proposed converter (a) Kcrit and K versus duty cycle, (b) load less factor (K) versus (Kcrit).
Mode 1 [0–t0]: same as for Mode 1 of DCMC2
Mode 2 [t0–t1]: same as for Mode 2 of DCMC2
Mode 3 [t0–t1]: same as for Mode 3 of DCMC2
Mode 4 [t2–t3]: Both MOSFETs Sw1 and Sw2 are in the off state, D2 and D3 remain on. L1 will discharge energy linearly due to the short discharging time required to charge C1, C2, and C3 with a large amount of power. L2 is an open circuit with no current, and D1 remains off. Both capacitors C2 and C3 accumulate a significant amount of energy from L1, while C4 starts to store a large amount of energy from L3 and L4. The current waveform of L3 and L4 will be the same but in opposite directions, without a constant current (I), and the load receives a substantial power supply from C5 through D4. The proposed converter for this mode is shown in Fig. 2c.
The voltage transfer gain of the proposed converter is calculated under two conditions when the converter operates in DCM and CCM.
To derive the voltage gain equation for the proposed converter operating in DCMC1, the volt-second balance equation is applied to L1, L2, L3, and L4 using Eqs. (1) and (7). This process yields Eqs. (19) and (20), which can be solved to obtain Eqs. (22) and (24). Additionally, during the steady state in DCMC1 at low duty cycle, the average voltage across C1 can be determined using Eq. (21). Equation (22) establishes the relationship between C2 and the input voltage source. In this context, (m1) represents the discharging time of L2, and its values can be obtained from Eq. (23), which is a function of (D, Vg, Vc2, and Vc3). (D1) denotes the discharging time of L3 and L4, and it can be calculated using Eq. (24).
Equations (25) and (26) represent the average and peak current through inductors L1 and L2, respectively. Equation (27) provides the average inductor current in L3 and L4. Meanwhile, Eqs. (28) and (29) deal with the peak inductor current in L3 and L4, respectively. To find the output current, we can calculate it by adding the currents from Eqs. (27), as demonstrated in Eq. (30). In this context, (LE) represents the equivalent inductors of L3 and L4, as shown in Eq. (31).
Equation (32) represents the output voltage of the proposed converter. The voltage gain equation for the proposed converter in DCMC1 can be obtained through Eq. (33), and solving this equation helps determine the load factor (K). Consequently, the voltage gain equation for the proposed converter as a function of K can be derived in Eq. (34). To find the critical load factor (Kcrit), we can use Eq. (35). The boundary condition of the proposed converter between CCM and DCM at Kcrit is shown in Eq. (36).
To derive the voltage gain equation for the proposed converter when it operates in DCMC2, volt-second balance equations are applied to L1, L2, L3, and L4 using Eqs. (17) and (7), which results in Eq. (37). Solving this equation leads to the results shown in Eqs. (38).
The value of (m) can be determined using Eq. (39), which depends on the values of L2 and C1. This approach reduces the current stress across the main switch as the load current increases. Additionally, it lowers the voltage stress across both the main and auxiliary switches, resulting in a reduction in voltage stress on all switched inductors, and diodes. When the charge in C1 reaches zero at (D-2m), the two diodes D2 and D3 will operate at ZVS, as shown in Fig. 13c. Equation (40) describes the voltage across C2. The discharging time of L3 and L4, denoted as (D1), can be determined from Eq. (41) after solving Eq. (38). Finally, the voltage gain equation of the proposed converter in DCMC2 is provided in Eq. (42).
By applying the volt-second balance equation to L1, L2, L3, and L4 in Eq. (43) at different times, the results can be found in (44) and (45) by substituting the value of Vc1 from Eq. (21) into Eq. (44). The voltage transfer gain of the proposed DC–DC converter when operating in CCM is given by Eq. (46). It can be observed that the voltage gain ratio equations of the proposed converter in DCM and CCM exhibit higher voltage gain ratios than those of previous DC–DC converters, as shown in Table 2.
In this section, the voltage stresses across the four power diodes and the voltage stresses across the power MOSFETs main and auxiliary are calculated both in DCM and CCM.
From Eq. (47), it can be determined that the voltage across D1 depends on the average voltage across C2, which is a very small value. Additionally, Eq. (48) provides information about the voltage across diodes D2 and D3 when the converter is operated in DCM, which is also very small and depends on the input voltage. Equation (49) allows us to calculate the voltage across MOSFET Sw1, which is equal to the input voltage as an average voltage. Equations (50) and (51) enable us to calculate the voltage across power MOSFET Sw2 and the voltage across D4, respectively. It can be seen that the voltage stress across diodes and switches is significantly reduced when the proposed converter is operated in DCMC1.
Equation (52) allows us to determine the voltage across D1 in CCM. During the time period (D-m), the voltage across D1 is reduced due to the resonant mode between L2 and C1. Additionally, inductor L2 remains uncharged and functions as an open circuit during this period. By utilizing Eq. (53), the voltage stress across Sw1 can be determined, and Eq. (54) can be used to find the voltage across diodes D2 and D3 in CCM. The voltage stress on power MOSFETs and power diodes is significantly reduced, resulting in decreased losses for the proposed DC–DC converter.
Furthermore, the voltage stress across D2 and D3 decreases, as both diodes operate with (ZVS) across them when one cell switched capacitor charge in C1 becomes zero from (D-2m < t < D), as shown in Fig. 11f. At the time (D-2m), the inductor current L2 flows through diodes D2 and D3, as depicted in Fig. 11c. Upon observing Fig. 4a,b, it becomes evident that the proposed converter operates in DCMC1 when the duty cycle is below 30%, provided that Kcrit (a critical factor) is lower than the load factor K. When the input voltage decreases to its minimum value, the converter operates in DCMC2 with a duty cycle above 30%. However, as the load increases and K exceeds Kcrit, the suggested converter can operate in CCM, as shown in Fig. 4, with a duty ratio exceeding 70%.
In this section, components for a 400 W prototype of the proposed DC–DC converter have been designed to validate the experimental results. The suggested converter comprises four inductors with very small values, five capacitors with low values, two power MOSFETs with low on-state resistance (Ron), and a simple gate drive circuit, along with four power diodes. The components have been designed to achieve a high voltage transfer gain, and their specifications for the 400 W model can be found in Table 1. To design the capacitors and inductors of the converter, Eq. (57) can be utilized to calculate the value of L1 with low ripple input current. Ripple of input current (\(\Delta iL_{1}\) ) can be found in Eq. (57). The resonant mode between C1 and L2 can be employed to find the value of L2 from Eq. (58). The values of inductors L3 and L4 can be obtained from Eq. (59), where L3 and L4 are in parallel connection. The values of C2 and C3 with very low ripple voltage can be derived from Eq. (60), and the value of C4 can be determined using Eq. (61). Finally, the value of C5 can be computed from Eq. (62) to achieve very low output voltage ripple.
Table 1 indicates that the utilization of a high switching frequency can decrease the size of inductors and capacitors in the proposed converter, leading to a lightweight and compact prototype with reduced costs. The specifications for the inductors include the use of flat wire with minimal internal resistance, effectively lowering losses in the proposed converter. Moreover, the power MOSFETs employed feature extremely low on-state resistance, thereby increasing voltage transfer gain and decreasing conduction power losses. In order to.
To validate the superior performance of the proposed converter in achieving a high voltage gain and low voltage stress across power devices, a comparison is conducted in this section between the proposed converter and previous DC–DC converters. The previous DC–DC converters were simulated using Matlab Simulink under the same conditions. Figure 5 shows that a higher voltage transfer gain is exhibited by the proposed converter compared to the previous converters. Additionally, the high gain of the proposed converter at a low duty cycle indicates several benefits, including higher efficiency, lower switching losses, low voltage stress across power devices, lower conduction losses with rms value current, and fewer capacitors and inductors required to achieve high voltage gain. The voltage gain of the proposed converter, approximately 13.5, can be calculated using Eq. (42) when the converter operates in DCM2.When looking at Fig. 6a, it can be seen that the voltage across the MOSFET device in the proposed converter is lower than that in the previous converters when compared to the gain ratio. In Fig. 6b, it can be observed that the voltage across the diode to the voltage source in the proposed DC–DC converter is lower than that in the previously used boosting converters.
Comparison of voltage transfer gain of converters.
(a) Voltage stress across power MOSFET versus voltage gain, (b) voltage stress across power diode versus voltage gain.
Table 2 presents a comparison between the proposed DC–DC converter and previous converters. The comparison focuses on the number of inductors, capacitors, diodes, switching frequency, input current, duty cycle percentage, and MOSFETs utilized in both the proposed and previous boosting converters. The results indicate that the previous boosting DC–DC converters are operated at a lower switching frequency than the proposed converter, resulting in higher inductor and capacitor values, as well as higher parasitic resistance. Additionally, the MOSFET's internal resistance at low switching frequency is high, leading to high conduction and switching losses. Moreover, the values of inductors and capacitors used in previous converters are larger, resulting in a larger, more costly, and heavier system. The previous boosting DC–DC converters can boost low voltage with a high voltage transfer ratio, but at an extremely high duty ratio. In contrast, the proposed converter can boost low voltage sources to a variable output voltage between 200 and 400 V at a lower duty ratio than previous boosting converters. The input current in the proposed converter is non-pulsating at both low and high duty cycles, whereas the converters in References2, 6, 10, 12 exhibit pulsating currents at low duty cycles. Finally, the proposed converter has a higher voltage gain compared to previous boosting DC–DC converters, making it more suitable for renewable energy systems that require variable and fixed high output voltage with a wider range in the duty ratio.
The proposed converter controller, as depicted in Fig. 7, employs double PI controllers. The first controller serves as the inner loop controller and is designed to regulate the load current, while the second controller functions as the outer loop controller and is responsible for regulating the output voltage. The PI voltage controller takes the error between the reference voltage and the output voltage as its input, and its output is the reference current, which is restricted to prevent excessive current draw from the converter. The error between the reference current and the output current is then fed into the PI current controller. The controller design process involves utilizing an equation that describes a PI controller with proportional and integral action control parameters KP and Ki. In Fig. 8(a), the proposed converter can maintain a constant output voltage of 400 V, regardless of input voltage changes from 40 to 30 V. This exemplary performance highlights the stability of the proposed converter and its capacity to deliver a consistent output voltage despite varying input voltage levels. In Fig. 8(b), the proposed converter can validate a constant output voltage at a fixed input voltage with variable load current. In Fig. 8(c), it can be observed that the proposed converter can verify variable output voltage ranging from 200 to 400 V at a fixed input voltage. This makes the proposed converter more suitable for a wide range of applications.
Voltage and current controller of proposed converter.
(a) Output of proposed converter at variable input voltage, (b) variable load current at fixed output and input voltage of the proposed converter, (c) variable load voltage 200–400 V at fixed input voltage.
The dual PI controller of the proposed converter demonstrates enhanced robustness and reliability, facilitating a quicker attainment of steady state. Furthermore, the proposed converter, equipped with current and voltage controllers, can achieve a wide range of duty ratios to supply high load current.
In this section, a prototype of the 400 W converter design was constructed to confirm the accuracy of the simulation and experimental outcomes, as depicted in Fig. 9a. The converter was subjected to experimental evaluation in the laboratory, as shown in Fig. 9b. Furthermore, the laboratory results were verified using MATLAB software under various conditions. It should be noted that non-ideal inductors and capacitors were used, and all parasitic resistances were accounted for in the proposed DC–DC converter.
(a) PCB design of the prototype proposed converter, (b) experimental prototype test of the proposed converter.
In Fig. 10a depicts a PWM generator producing a 33% duty ratio with an output voltage of 413 V. The voltage source is 40 V, and the voltage across capacitors C2 is 60 V at a load current of 1 A. Figure 10b displays the current flowing through inductors L1, L2, L3, and L4. It is evident that iL1 experiences no pulsation at the low duty cycle of 33% with very low ripple input current. Current L2 discharges to C2 and C3 during period (m1), while the currents through L3 and L4 have the same shape but in reverse directions. Figure 10c shows the voltage across inductors. It is noticeable that the voltage across L2 is Vc2 during the off state of period (m1), and it is zero from (D + m1 < t < Ts). Figure 10d shows the current through capacitors, while Fig. 10e displays the voltage across power MOSFETs and diodes of the proposed converter. The voltage stress across SW1 is significantly reduced, and the average voltage is equal to the input voltage. The voltage across Sw2 is equal to the output voltage during the very short period (D < t < D1) and Vc3 voltage during the very long time (D1 < t < Ts). Moreover, the voltage across D1, D2, and D3 is equal to Vc3. Figure 10f illustrates the current through MOSFETs and power diodes. It can be observed that ISW1 equals iL1 and iL2, while the current through ISW2 is equal to capacitor current C2. Furthermore, the current through D2 and D3 equals L1 and L2 current during the off state.
Proposed converter operation at DCMC1 (a) gate source voltage at D = 0.33, Vo = 413 V, Vc2 = 60 V, Vg = 40 V and load current Io = 1 A, (b) iL1, iL2, iL3 and iL4, in DCMC1, (c) VL1, VL2, VL3 and VL4, (d) capacitors Current Ic1, Ic2, Ic3, Ic4 and Ic5, (e) voltage stress, Vsw1, Vsw2 and VD1, VD2, VD3 and VD4, (f) Isw1, Isw2 ID1, ID2, ID3 and ID4.
During this experiment, the voltage transfer gain equals 10 at a duty cycle of 0.33. The proposed converter exhibits zero pulsating input current at very low duty ratios. Additionally, the voltage across power MOSFETs and diodes is significantly reduced, indicating very small values. Hence, the proposed DC–DC converter is more suitable for renewable energy sources (RES) applications. After incorporating all parasitic components, the simulations show that the proposed converter operates in DCMC2. At an input voltage of 20 V, Fig. 11a demonstrates that the converter produces an output voltage of 200 V, and the voltage across capacitor Vc3 is approximately 29 V at a load current of 1 A. Figure 11b displays the current through power switch SW1, revealing that the stress current through SW1 is reduced because charge in C1 becomes zero at (D-2m) and L2's charge makes D2 and D3 turn on to charge L3 and L4. Figure 11c shows the voltage across D2 and D3. It can be seen that the voltage across D2 and D3 is totally reduced when L2 and C1 work in resonant mode. So, both of them opearte in ZVS during this time (D-2m) as shown in Fig. 13c. Meanwhile, L2 will pass current through them at (D-2m) < t < Ts and will work as ring to charge L3 and L4 through Sw2. Figure 11d shows inductor current when the converter operates in CCM, and Fig. 11e shows inductor current in DCMC2.
(a) Gate source voltage at D = 0.5, Vo = 200 V, Vc2 = 29 V, and Vg = 20 V, (b) Isw1, at zero charge of C1 and show the current reduction of Sw1 after (D-2m), (c) VSW1,VSW2 and VD1,VD2,VD3 and VD4, (d) current through inductors iL1,iL2,iL3 and iL4, at CCM, (e) current through inductors at DCMC2, (f) current through capacitors IC1 and IC2 and current through Sw1.
Figure 11f shows that the current through capacitors Ic1 and Ic2, as well as the current through Sw1, reduce when the charge in capacitor C1 becomes zero at (D-2m). In terms of experimental test results, Fig. 12a illustrates the current through inductors L1 and L2 when the converter operates in DCMC1. Figure 12b illustrates the current through inductors L2 and L3 when the converter operates in DCMC1. Figure 12c shows the MOSFETs current ISW1 and ISW2. Figure 12d,e show the voltage across switches Vsw1 and Vsw2. In Fig. 12f, the current through D2 and D3 can be observed when L2 discharges current through them due to the charge in capacitor C1 becoming zero at (D-2 m). It shows that D1 operates with low current stress, and during this time, inductor L2 works as an open circuit. The voltage across D1 is equal to Vc3. Figure 13a displays the inductor current when the converter operates in DCMC2. In Fig. 13b, the voltage across D4 is shown.
(a) Inductors currents iL1, iL2 at DCMC1, (b) inductors currents iL3 and iL4, at DCMC1, (c) power MOSFETs current Isw1, Isw2, (d, e) voltage across power MOSFET Vsw1 and Vsw2, (f) current through D2,D3 and Voltage across D1.
(a) Inductors currents iL1,iL2 at DCMC2, (b) VD4, (c) current through D2, D3 and voltage across D2 and D3, (d) current through capacitors C1 and C2,C3, (e) Vo = 200 V at load current 1 A, (f) load voltage VO = 400 V. (g) Vc1, (h) Vc2 and Vc3, (i) dynamic response of the proposed converter at load change from 280 to 200 w.
Figure 13c demonstrates the voltage across D2 and D3, revealing that they experience ZVS during the on state from (D-2m) when charge in C1 becomes zero during (D-2m). During this time, L2 discharges current to charge L3 and L4 through Sw2, reducing the voltage across the power MOSFET and diodes. This method enhances the efficiency and performance of the converter. Furthermore, the open circuit state of inductor L2 minimizes losses from the converter's passive components. Figure 13d shows the currents through capacitors IC1 and IC2. Figure 13e displays the output voltage of the proposed converter, Vo = 200 V, at a load current of 1 A, with D = 50%. Figure 13f shows the load voltage Vo = 400 V at D = 33%. In Fig. 13g, the voltage across C1, equal to 25 V, is depicted, while Fig. 13h shows the voltage across C2 at a low duty cycle, which is equal to 54 V. The dynamic response of the proposed converter at load changing from 280 to 200 w is shown in Fig. 13i.
As a result, when the input voltage reaches its minimum value, the proposed converter can operate with high efficiency. It utilizes D1 power diode, which operates with low current stress and low voltage stress, and diodes D2 and D3, which work at low voltage stress during the on state, thus reducing the number of passive components. Additionally, this design enhances the efficiency and reliability of the proposed converter for renewable energy systems that require high output fixed and variable DC voltages. Furthermore, the voltage stress across Sw1 and Sw2 is significantly reduced when the proposed converter operates in DCMC2 at 400 W. Moreover, the current and voltage stress of all power diodes are significantly reduced, resulting in a significant reduction in total power losses. Additionally, the current of Sw1 is significantly reduced when a single cell of switched inductor capacitors is added and operates in the resonant mode.
The proposed converter comprises five capacitors, four inductors, two power switches, and four diodes. However, it should be noted that these components are not ideal, meaning that each component has its internal resistance that affects its performance. For instance, the internal resistance of an inductor increases as the value of the inductor increases. The internal resistance of each inductor is denoted as rl1, rl2, rl3, and rl4, while the equivalent series resistances of capacitors are rc1, rc2, rc3, rc4, and rc5. Additionally, the power diode has two power losses: one due to its internal resistance rd and the other due to its forward voltage Vf. Other power losses occur due to conduction and switching losses of the power MOSFET devices. Therefore, all of these losses should be taken into account when considering the proposed converter. The internal resistances of all the inductors, capacitors, power diode, and MOSFETs can be seen in Fig. 14.
To determine the total power losses of the proposed converter, it is necessary to calculate the RMS current for the inductors, capacitors, power MOSFET, and diodes in both on and off states. Equation (63) represents the general equation for RMS current. Equations (64) and (65) can be utilized to obtain the RMS current through SW1 and SW2 during the on state. During the on state, the RMS current through D1, which is equal to the RMS current through inductor L2 during the period (0 < t < D-m), can be calculated using Eq. (66). Equation (67) provide the RMS current for D2 and D3 and, Eq. (68) provide the RMS current for D4, and Eqs. (69), (70), (71),and (72) can be employed to determine the RMS currents for capacitors C1, C2, C3, C4 and C5, respectively.
Equations (73) and (74) describe the RMS current flowing through the MOSFETs. To calculate the RMS currents flowing through the power diodes, you can use Eqs. (75), (76), and (77). Equations (78), (79), and (80) provide the RMS current flowing through inductors L1, L3, and L4 respectively. Finally, we can determine the RMS current through capacitors C1, C2, C3, C4, and C5 using Eqs. (81), (82), (83), and (84), respectively.
The proposed converter with internal resistance in passive and active components.
To determine the conduction losses of the power MOSFET in the proposed converter, (RMS) current is multiplied by the value of the on state resistance of the MOSFET.
The power conduction losses of MOSFETs Sw1 and Sw2, Pcd1 and Pcd2, can be obtained from Eqs. (85) and (86). Equation (82) provides a means to calculate the power switching losses, PSWL1 and PSWL2, of MOSFETs Sw1 and Sw2. These losses can be obtained using the output capacitor of the MOSFET, Co, and the switching frequency, Fs. The total power losses of MOSFETs PSWL1 and PSWL2 can be obtained by adding Eqs. (85), (86), (88), and (89) as a result, resulting in Eq. (90).
In order to accurately calculate the power losses incurred by the four diodes in the converter, it is important to take both types of losses into consideration. To determine the power losses due to Vf, one can use Eq. (91) to calculate the average current flowing through diodes, and then multiply this result by Vf and the power losses (Pvf) caused by the forward voltage. On the other hand, Eq. (92) can be used to calculate the diode power losses due to rd, while Eq. (93) is used to determine the power losses due to Vf. Finally, to obtain the total power losses (TPDL1, TPDL2, TPDL3, TPDL4) across all four diodes, Eq. (94) can be used to add up all losses in the power diode.
By utilizing Eqs. (95) and (96), it is possible to determine the power losses (PL) and (PC) in the inductors and capacitors, respectively. The losses associated with the proposed converter can be categorized into four types: MOSFET losses, diode losses, inductor losses, and capacitor losses. Equation (97) can be employed to calculate the total power loss (TPLPC) of the converter by adding the power losses of the power MOSFETs (TPLCS1,2), the total power losses of the diodes (TPDL1,2,3,4), and the losses in the inductors and capacitors (TPL1,2,3,4 and TPC1,2,3,4,5) respectively. The efficiency of the proposed converter can be determined by Eq. (98). Clearly, SiC MOSFETs with very low on-state resistance are the optimal choice for minimizing conduction losses. Additionally, utilizing inductors with low internal resistance values will further improve the performance and efficiency of the proposed converter.
Figure 15a,b illustrate the conduction power losses of MOSFETs across different input and output voltages. It showed that, the conduction power losses of both MOSFET with a small value of internal resistance are decreased.
(a, b) Conduction power losses of MOSFET Sw1 and Sw2at variable input and output voltage, (c) output voltage of the proposed converter at different switching frequency at D = 33%, (d) total power losses in proposed converter.
Therefore, the proposed converter utilizing SiC MOSFET with Ron 7 m demonstrated minimal power conduction losses even with varying duty cycles, resulting in higher efficiency than previous DC–DC converters. The implementation of WBG MOSFETs is expected to further reduce both conduction and switching losses, leading to a substantial increase in the efficiency of the proposed converter.
In Fig. 15c, it can be seen that the proposed converter's output voltage varies with different switching frequencies. The new design of the proposed converter enables high output voltage at high switching frequencies with very low values of inductors and capacitors. However, the load voltage of the proposed converter significantly reduces when the switching frequency is reduced to 25 kHz. This means that the proposed converter can supply 400 V to a 400 W load at a duty cycle of 33% by utilizing high switching frequency, resulting in a small size and low cost of the proposed converter. Figure 15d displays the overall power losses of the proposed converter, taking into account various input and output voltages. One significant observation is that the converter experiences a loss of 4% at 400 W when the input voltage is around 40 V. The proposed converter demonstrates remarkable efficiency when supplying high load current at a low duty cycle within the input voltage range of 20–40 V.
In Fig. 16a,b, the proposed converter's efficiency is shown under variable input voltage at an output voltage 200 V. The results indicate an efficiency of around 96% at 40 V input voltage. In Fig. 16c,d, the efficiency of the proposed converter is shown for variable input voltage at an output voltage of 400 V. The results indicate an efficiency of approximately 96% at 40 V input voltage.
(a–d) Efficiency of the proposed converter at variable input and output voltage versus load current and duty cycle respectively.
Therefore, the suggested converter is capable of increasing a low input voltage to a high output voltage while providing a high load current at variable input voltage without any input current pulsation at a low duty cycle with high power density efficiency. In addition, the proposed DC–DC converter can supply variable high-output voltage between 200 and 400 V, making it more suitable for a wide range of applications.
In conclusion, this paper has introduced a highly optimized DC–DC converter employing the innovative modified switched inductor-capacitor (MSLSC) technique, which represents a significant advancement in the field of (RES). The MSLSC-based converter offers several remarkable advantages that make it a promising solution for various applications. One of the key contributions of this research is the introduction of the modified switched inductor (MSL1) and capacitor in series with diodes, which operate in a resonant mode. This design effectively reduces current stress across the main switch, diodes, and inductors, thereby enhancing the overall reliability of the converter. Additionally, the integration of modified switched inductors (MSL2) and capacitors with auxiliary switches further boosts voltage gain and reduces voltage stress on critical components. In addition, the proposed DC–DC converter can supply variable high-output voltage between 200 and 400 V, making it more suitable for a wide range of applications.
The experimental results, including the construction of a 400 W printed circuit board (PCB), validate the simulation findings, demonstrating a remarkable efficiency of approximately 96.2% at 400 W with a 40 V input voltage. This level of efficiency is a significant achievement, especially for RES applications, where converting low input voltages to high output voltages is crucial. Furthermore, the elimination of pulsating input current and reduced voltage stress on power devices highlight the practicality and reliability of the proposed converter. By leveraging SiC MOSFETs and high switching frequencies, this converter minimizes switching losses, component values, and circuit size while maximizing efficiency and performance.
In summary, the optimized DC–DC converter based on the MSLSC technique represents a groundbreaking development in RES. Its exceptional efficiency, voltage stress reduction, and adaptability to various duty cycles make it a promising candidate for enhancing the efficiency and reliability of RES applications. This innovation holds great potential for contributing to the advancement of sustainable energy solutions.
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School of Automation, Northwestern Polytechnical University, Xi’an, 710072, China
Ammar Falah Algamluoli & Xiaohua Wu
Electrical Engineering Technical College, Middle Technical University, Baghdad, Iraq
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A.A.: Formal analysis, Investigation, Methodology, Writing – original draft, Writing – review & editing. X.W.: Conceptualization, Supervision. M.F.: Proofreading and figures.
Correspondence to Ammar Falah Algamluoli.
The authors declare no competing interests.
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Algamluoli, A.F., Wu, X. & Mahmood, M.F. Optimized DC–DC converter based on new interleaved switched inductor capacitor for verifying high voltage gain in renewable energy applications. Sci Rep 13, 16436 (2023). https://doi.org/10.1038/s41598-023-42638-5
DOI: https://doi.org/10.1038/s41598-023-42638-5
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